Hardware Trojans : Taxonomy and Detection Methods

Julien Francq
Lundi 08 Juil 2013

Nowadays, for financial reasons, most of the Integrated Circuits (ICs) are designed, manufactured and tested in foreign countries. It is thus difficult to secure all the IC design flow: nothing can prevent from the insertion of any malicious and deliberate change to the IC (also called Hardware Trojans, HTs) that may cause unwanted effects and potentially damages in many sensitive applications (avionics, space, military devices, communication, industry, nuclear plants, etc.).

This presentation proposes first to show a taxonomy of the different HTs of the literature. We will see that this bestiary is very big. Then, we will detail the detection methods of the state-of-the-art with their limitations.

Destructive HT detection methods mainly consist in reverse-engineering ICs before deployment, which is very costly and does not guarantee 100% detection rate. Moreover, non-destructive HT detection methods (logic test, side-channel analysis, etc.) have also to face challenges (process variation noise, measurement noise, low controllability and observability of nodes, etc.). Finally, the speaker will show the French funded R&D project HOMERE (Hardware Trojans: Threats and Robustness of Integrated Circuits), which will try to progress beyond the state-of-the-art.